Hi Andreas
Thanks a lot for pointer. I have been experimenting with your suggestion. I
have few questions.
*Question 1:*
In configs/common/Caches.py. configuration is done as follows:
----------------------------------------
class L1Cache(BaseCache):
assoc = 2
hit_latency = 2
response_latency = 2
mshrs = 4
tgts_per_mshr = 20
is_top_level = True
----------------------------------------
But when I print the values of variables used in isFull function (in
src/mem/cache/mshr_queue.hh) , I see following
----------------------------------------
16338315506500: system.cpu0.icache: Packet: MasterId=cpu0.inst
16338315506500: global: Number of allocated 1
16338315506500: global: Number of numEntries 8
16338315506500: global: Number of numReserve 4
16338316046500: system.cpu0.dcache: Packet: MasterId=switch_cpus0.data
16338316046500: global: Number of allocated 1
16338316046500: global: Number of numEntries 9
16338316046500: global: Number of numReserve 4
----------------------------------------
How come these values are different from those values? Am I looking at
wrong place?
*Question 2:*
As per your suggestion, I am trying to configure the MSHR per core in
configuration file itself. The fs.py import from CacheConfig.py:
----------------------------------------
for i in xrange(options.num_cpus):
if options.caches:
print i
icache = icache_class(size=options.l1i_size,
assoc=options.l1i_assoc,
mshrs=5)
dcache = dcache_class(size=options.l1d_size,
assoc=options.l1d_assoc)
----------------------------------------
So configuring mshrs over here will overwrite other values. Is this the
correct place or were you referring to some other place?
ᐧ
On Thu, Jul 16, 2015 at 4:03 AM, Andreas Hansson <andreas.hans...@arm.com>
wrote:
> Hi all,
>
> The best way to customise your L1 instances is in the config script
> itself. If you use fs.py, I’d suggest to do it there.
>
> Andreas
>
> From: gem5-users <gem5-users-boun...@gem5.org> on behalf of Prathap
> Kolakkampadath <kvprat...@gmail.com>
> Reply-To: gem5 users mailing list <gem5-users@gem5.org>
> Date: Thursday, 16 July 2015 00:00
> To: gem5 users mailing list <gem5-users@gem5.org>
> Subject: Re: [gem5-users] MSHR Queue Full Handling
>
> Hello Davesh,
>
> I think it should be possible by passing the desired L1 MSHR setting for
> each core, while instantiating the dcache in CacheConfig.py
> Also look at the BaseCache constructor, to see how these parameters are
> being set.
>
>
> Thanks,
> Prathap
>
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Have a great day!
Thanks and Warm Regards
Davesh Shingari
Master's in Computer Engineering [EE]
Arizona State University
davesh.shing...@asu.edu
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