Hi all,
I simulated 2-core O3 X86 system in FS with classic memory and Ruby. I am trying to transfer gem5 output stats (ITLB and DTLB accesses) to McPAT. I couldn't find any stats for TLB accesses in gem5 stats file when I use Ruby, except for IFETCH stall cycles for TLB. However when I use classic memory for same system, I could see walker_cache accesses for ITLB and DTLB. >From config.ini files, I realized that walker_ports in classic memory are >connected to Walker_cache (for ITLB and DTLB separately) where page table >information seems to be stored. But in Ruby walker_ports are connected to Ruby >Sequencer of L1 controller. The thread attached below confirms that Ruby does >not model walker_cache to store pagetable information. http://comments.gmane.org/gmane.comp.emulators.m5.users/12287 All I need are ITLB and DTLB stats from gem5 to integrate McPAT. Is there any way to extract ITLB and DTLB accesses from gem5 ? Any insights on this would be of great help! Thanks, Yaswanth Akaveeti
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