Fernando Endo <fernando.endo2 <at> gmail.com> writes: > > > Hello, > Note that, in the SE mode, there are no TLB stats. In FS there are. > > Regards, > > > --Fernando A. Endo, Post-docINRIA Rennes-Bretagne AtlantiqueFrance > > 2015-12-21 14:53 GMT-02:00 Yaswanth Akaveeti <yaswanth.akaveeti <at> mail.mcgill.ca>: > > > > > > > Hi all, > > I simulated 2-core O3 X86 system in FS with classic memory and Ruby. I am trying to transfer gem5 output stats (ITLB and DTLB accesses) to McPAT. I couldn't find any stats for TLB accesses in gem5 stats file when I use Ruby, except for IFETCH stall cycles > for TLB. However when I use classic memory for same system, I could see walker_cache accesses for ITLB and DTLB. > > From config.ini files, I realized that walker_ports in classic memory are connected to Walker_cache (for ITLB and DTLB separately) where page table information seems to be stored. But in Ruby walker_ports are connected to Ruby Sequencer of L1 controller. > The thread attached below confirms that Ruby does not model walker_cache to store pagetable information. > <a title="http://comments.gmane.org/gmane.comp.emulators.m5.users/12287 > Ctrl+Click or tap to follow the link" href="http://comments.gmane.org/gmane.comp.emulators.m5.users/12287"; target="_blank">http://comments.gmane.org/gmane.comp.emulators.m5.users/12287 > > All I need are ITLB and DTLB stats from gem5 to integrate McPAT. Is there any way to extract ITLB and DTLB accesses from gem5 ? Any insights on this would be of great help! > > Thanks, > Yaswanth Akaveeti > > > > > > _______________________________________________ > gem5-users mailing listgem5-users <at> gem5.orghttp://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > > > > _______________________________________________ > gem5-users mailing list > gem5-users <at> gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Hi Fernando, Thanks for your kind response. I created checkpoints using timing cpus for a 2-core X86 system in FS mode. I restored from the checkpoints using the following command: build/X86_MOESI_hammer/gem5.opt configs/example/fs.py \ --outdir=./2-core/restore-tot_2-c-timing-to-Detailed-ruby/ \ --script=./parsec-scripts/fluidanimate_2c_test.rcS --num-cpus=2 \ --checkpoint-dir=/fluid-check/2-core/check_total_2-core-timing/ \ --checkpoint-restore=9 --rel-max-tick=2428547643 --cpu-type=detailed \ --restore-with-cpu=timing --ruby --l1i_size=32kB --l1d_size=32kB \ --topology=Mesh --mesh-rows=1 --num-dirs=2 In the stats file, the tlb stats that I could find are: -system.switch_cpus0.fetch.ItlbSquashes -system.switch_cpus0.fetch.TlbCycles -system.switch_cpus1.fetch.ItlbSquashes -system.switch_cpus1.fetch.TlbCycles But I would like to extract ITLB and DTLB accesses from gem5 output which I cannot find. Also I went through the source code files arch/x86/tlb.cc, arch/x86/tlb.hh to find if there are any statistics related lines. But I could not find any portion of the code with "regstats()". Interestingly, I found "regstats()" in arch/alpha/tlb.cc files which has different statistics like fetch_accesses, fetch_misses in the file. I think that Alpha ISA has ITLB and DTLB stats while X86 does not. Please correct me if I am wrong. And could you please be more specific about the stats you were talking about in your reply about TLB stats. Please let me know any insights you have on this. It would be of great help! Thank you, Yaswanth _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
