Hi Muhammad,
I am afraid, I haven't looked much in the code for MESI_Two_Level, I remember I run into the same issue as you and I figured what was the problem but I haven't been able to find some time to fix it. >From what I can tell you're looking the right direction. It seems like the >problem is in the response path for devices behind DMA controllers. As for the >question on address ranges, If the problem is indeed in the response, the >routing can only rely on the source node id rather than the address of the >destination. I am sorry I can't be more helpful but hopeful someone with more experience in ruby can chime in. Thanks, Nikos ________________________________ From: gem5-users <gem5-users-boun...@gem5.org> on behalf of SHARJEEL KHILJI <sharjeelsaeedkhi...@gmail.com> Sent: 21 June 2017 13:51:42 To: gem5 users mailing list Subject: Re: [gem5-users] Invalid transition DMA controller in NoC Hi Nikos, I have tried to add the support for multiple DMA controllers to MESI Two Level by using the Machine ID of the DMA controllers. The Node ID in machine ID is the version of the machine. As per config.ini i get three different DMA controllers with versions 0 1 2. Now the Node ID is based upon the m_version of the controllers. I am using this Node ID to route the request to the particular DMA controller. What I am doing is that I broadcast response from Directory controller to all DMA controllers. Then at DMA controller in the inport (dmaResponseQueue_in) I match the Node ID of the controller with the Node ID of the response (the Node ID in the response is the same as the one in the request). If a match is found then an event of DATA or ACK is generated otherwise not. But still I get an invalid transition (The ACK gets delivered to the wrong DMA controller). I want to ask that Node ID is based upon the version of the controllers and is unique for all controllers right? If so then why the ACK still gets delivered to wrong DMA. What I assume is that Node ID is unique for all DMA controllers and is based upon m_version (version in config.ini). Now the version is different for all three controllers. If this assumption is correct then Node IDs should be (0 1 2). Which will not result in any overlap or wrong transition. Any suggestions? Any one? Another thought is that I can add address ranges to DMA Controller is this possible? best regards, Muhammad On 12 June 2017 at 13:10, Nikos Nikoleris <nikos.nikole...@arm.com<mailto:nikos.nikole...@arm.com>> wrote: Hi Muhammad, If I remember correctly, MESI_Two_Level lacks support for multiple DMA controllers. The request message does not store the source of the packet and the response doesn't reach the right DMA controller. If you have a look at MOESI_CMP_directory, the DMA controller (MOESI_CMP_directory-dma.sm) encodes the source node in the Requestor and RequestorMachine fields which are then used to route the response. It shouldn't be too hard to add something similar for the MESI_Two_Level protocol. Nikos ________________________________ From: gem5-users <gem5-users-boun...@gem5.org<mailto:gem5-users-boun...@gem5.org>> on behalf of SHARJEEL KHILJI <sharjeelsaeedkhi...@gmail.com<mailto:sharjeelsaeedkhi...@gmail.com>> Sent: 12 June 2017 07:56:51 To: gem5 users mailing list Subject: [gem5-users] Invalid transition DMA controller in NoC Hi, I am running the following system, scons build/ARM/gem5.debug PROTOCOL=MESI_Two_Level ./build/ARM/gem5.debug --debug-flags ProtocolTrace configs/example/fs.py --l1d_size=32kB --l1i_size=32kB --num-l2caches 4 --l2_size=1MB --cacheline_size=64 --machine-type=VExpress_GEM5_V1 --kernel /home/khilji/gem5/m5/system/binaries/vmlinux-aarch32 --disk-image /home/khilji/gem5/m5/system/disks/arm-ubuntu-natty-headless.img --dtb-filename /home/khilji/gem5/m5/system/dtb/armv7_gem5_v1_4cpu.dtb --num-cpus=4 --ruby --num-dirs=4 --network=garnet2.0 --topology Mesh_XY --mesh-rows 2 --mem-size 1GB --cpu-clock 1GHz While running this in debug, and booting the linux I get the following invalid DMA transition. When DMA controller receives the read request from the DMA sequencer it moves to the busy read state but when input response (Data) is received from (Directory/or PUTX L1) the DMA has already returned to ready state before Data event occurs. There are three DMA controllers (equal to dma ports) in the system as specified in config.ini. Is this because of the fact that one of the controllers issues the read request to directory and all of the controllers receive the response? and then those who have not issued the request receive the response while in ready state which results in exception. Following is the protocol trace 646885666000 2 L1Cache Load M>M [0xbda99a00, line 0xbda99a00] 646885667000 2 Seq Begin > [0x80359d7c, line 0x80359d40] IFETCH 646885668000 2 Seq Done > [0x80359d7c, line 0x80359d40] 1 cycles 646885668000 2 L1Cache Ifetch S>S [0x80359d40, line 0x80359d40] 646885670500 1 DMA ReadRequest READY>BUSY_RD [0xbf040000, line 0xbf040000] 646885676000 0 Directory DMA_READ M>M_DRD [0xbf040000, line 0xbf040000] 646885681500 0 L2Cache MEM_Inv MT>MT_I [0xbf040000, line 0xbf040000] 646885681500 0 L2Cache MEM_Inv MT_I>MT_I [0xbf040000, line 0xbf040000] 646885685500 2 L1Cache Inv M>I [0xbf040000, line 0xbf040000] 646885694000 0 L2Cache WB_Data MT_I>M_I [0xbf040000, line 0xbf040000] 646885700000 0 Directory Data M_DRD>M_DRDI [0xbf040000, line 0xbf040000] panic: Invalid transition system.ruby.dma_cntrl0 time: 1293771411 addr: 3204710400 event: Data state: READY Memory Usage: 1584496 KBytes Program aborted at tick 646885705500 Any suggestions? best regards, Muhammad IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. 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