Hi all, I recently switched from gem5/x86 to gem5/RISCV due to some advantages of this ISA.
I'm getting some weird simulation results and I realized my compiler was generating instructions for the compressed RISCV ISA extension (chp 12 in the user level ISA specification <https://riscv.org/specifications/>). The weirdness disappears when I use *--march* to remove these extensions. *So the question is: does gem5/RISCV support this ISA extension? *If so, I can share the weird results (maybe I'm missing something) but basically a wide-issue O3 processor fetches only max 1 instruction/cycle when it should probably be fetching more. If it doesn't support then it's all OK, I just find it a bit weird that the program executes normally with no warnings whatsoever. Best regards, -- Marcelo Brandalero PhD Candidate Programa de Pós Graduação em Computação Universidade Federal do Rio Grande do Sul
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