Hello, and welcome to the gem5 mailing list :). I suggest, at least as a first pass, using the classic caches, not Ruby. You can check out the Learning gem5 book (learning.gem5.org) to see examples of how to create different kinds of systems that don't necessarily match what's in se.py. The classic caches have an option to be "mostly inclusive" and "mostly exclusive" which might do what you need.
I don't know if anyone has tried to have separate L2 instruction and data caches. However, this might "just work" with the classic caches assuming you have separate instruction and data busses (this should be possible). I suggest drawing the system you want to simulate on paper, then trying to create the configuration in gem5. If you want to investigate modifying the cache coherence protocol, or your investigation depends on high-fidelity modeling of the on chip network, then you should use Ruby. In this case, you'll probably have to write a new coherence protocol. You might be able to use other coherence protocols (e.g., MESI_Two_Level) as a starting point, or you might have to develop a new one from scratch (See Part 3 of Learning gem5 for details). Cheers, Jason On Wed, Jul 10, 2019 at 9:41 AM Armel Jeatsa <toulepiar...@gmail.com> wrote: > Hello, > I am relatively new in gem5 simulator, i have to design a multiprocessor > architecture with two levels of caches composed of: > > - At level 1: the usual L1i and L1d caches > - At level 2 (shared by all processors): L2i and L2d caches, L2i > inclusive with L1i, and L2d non-inclusive with L1d. > > What is the best solution? Use *Ruby *and* Slicc*, or just *Python* and > *C++*. How should I proceed in this case? > I ask this question because the *System* object in gem5 seems to only > accept an L2 bus. > Thank you in advance. > -- > *JEATSA TOULEPI Armel* > Étudiant En Génie Informatique > Tel: +237 650771894 / 655296800 > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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