Shehab, sorry for the delay, I had to check a few things about this, First, are you aware that there is a not-yet-merged patch that implements a two level TLB at: https://github.com/giactra/gem5/commit/3022ecc8a06a9182b2cf1936941901a785c1b21d ?
It hasn't been merged because we noticed that it broke Linux boot I think. But we would like to merge it in the following months. I'm not sure why Ruby vs classic would matter since the TLB sits behind caches anyways? I believe that model will work for either classic or Ruby. ________________________________ From: Shehab Elsayed via gem5-users <gem5-users@gem5.org> Sent: Tuesday, June 23, 2020 12:20 AM To: gem5 users mailing list <gem5-users@gem5.org> Cc: Shehab Elsayed <shehaby...@gmail.com> Subject: [gem5-users] 2 level TLB in ARM Full System with Ruby Hello All, I was wondering if there is a way to simulate a system with 2 levels of TLBs in full system simulation with ruby for ARM? I have seen other examples that use the classical memory model and use a cache as the second level TLB. Is there something similar that can be done in Ruby memory system. Can I use a standalone RubyCache as the second level TLB? Thank you very much in advance. Best Regards, Shehab
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