Hi. I have another question. My goal is to specify the memory that cpu uses, just like the previous question.
instead of checking the cpu_id of packets on the memory controller and sending them to different memory, I thought it would be better to add a certain value to the address value of each cpu's memory access request. Also, if gem5 put the workload that each cpu has in different memory at the beginning of the simulation, it will work without any problems. So, My questions are 1. where is the workload loaded to memory in gem5 simulator? 2. where cpu's memory access request is generated? 2020년 11월 19일 (목) 오후 9:10, Alex Freij <atfr...@ncsu.edu>님이 작성: > Hi, > > The files you want to look at for the memory access are src/mem/ > dram_ctrl.cc/.hh and src/mem/DRAMCtrl.py for issuing requests from the > memory controller. The memory access itself is performed in > DRAMCtrl::accessAndRespond, with a call to access() which is defined in > src/mem/abstract_mem.cc. > > This may have changed with recent gem5 updates but I don't think there is > a field to identify the requesting core so you can differentiate between > them, but perhaps adding a field in the packet class definition and > assigning the threadID would help you do that. > > Sincerely, > > - Alex >
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