Hi Leon, I believe you're correct. When there is a TLB hit, it's up to the *CPU model* to model the latency of the TLB access. I think this implementation was designed this way to give flexibility to the CPU models. Since the TLB is deeply embedded in the pipeline, we wouldn't want to always have a 1 cycle latency for the TLB. On the other hand, when there is a miss (in FS mode), the page table walker will model the correct delay.
Cheers, Jason On Wed, Apr 21, 2021 at 6:38 AM Leon Zhao via gem5-users < [email protected]> wrote: > Hi all, > > While I'm doing some research about how TLB is emulated in gem5 the other > day, I noticed that TLB costs no ticks, which is quite unusual. > I tried printing current tick before and after (xxx is where I set in my > print declaration): > (1) src/cpu/o3/lsq_impl.hh > void LSQ<Impl>::LSQRequest::sendFragmentToTranslation(int i) { > xxx > the original function body > xxx > } > (2) src/cpu/o3/fetch_impl.hh > DefaultFetch<Impl>::finishTranslation(const Fault &fault, const > RequestPtr &mem_req) { > ... > xxx > if (fault == NoFault) { > .... > fetchedCacheLines++; > xxx > ... > } > ... > } > > However, in both cases, both print functions printed the same tick number > (starting from the very beginning). Is this normal or I found the wrong > places to implant printf's or there's some misunderstanding about my > perspective? > > Here is a sample of what's left on my console: > > !>> TLB starts @ tick=86592000 > !>> TLB ends @ tick=86592000 > !>> TLB starts @ tick=86593000 > !>> TLB ends @ tick=86593000 > !>> TLB starts @ tick=86597000 > !>> TLB ends @ tick=86597000 > > Any pointers would do. Thanks in advance. > _______________________________________________ > gem5-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s >
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