On 3/9/2023 5:44 PM, Ayaz Akram wrote:
Hi Eliot,
gem5 splits the memory system modeling into two parts: 1) the memory controller and 2) the memory
interface. The memory interface can be a DRAMInterface or NVMInterface and provides many parameters
that are configured to achieve a specific memory device model (e.g., DDR4, GDDR5). The available
configuration parameters and their values for different devices can be found in
src/mem/DRAMInterface.py (this file provides definitions of different timing parameters).
The memory controller usually is agnostic to the actual timing parameters used by a memory
interface and relies on a fixed interface to talk to the device. However, we currently have three
types of memory controllers in gem5: MemCtrl (which can be used with a single memory interface of
any type), HeteroMemCtrl (which can be used with two memory interfaces at the same time, a DRAM and
an NVM interface), and HBMCtrl (which is used with two HBM2 interfaces, where each interface is
modeling a pseudo channel).
Some references that might be helpful to understand gem5's memory system model
include:
- gem5 workshop presentation should help explain the NVM model of gem5:
https://www.gem5.org/2020/05/27/memory-controller.html
<https://www.gem5.org/2020/05/27/memory-controller.html> (Also, one of the videos in this
presentation discusses the refactorization of the original mem controller into mem controller and
memory interface).
- Minutes 37-52 of this gem5 bootcamp presentation:
https://www.youtube.com/live/hciJ9rguats?feature=share
<https://www.youtube.com/live/hciJ9rguats?feature=share>
- The original gem5 memory controller model paper:
https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6844484
<https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6844484>
-Ayaz
Wonderful! thank you, Ayaz! I had found the .py files, but the bigger
picture explanation and the presentation, etc., will be really helpful
as we try to set up a realistic configuration!
Best wishes - Eliot
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