Right now my controller object just intended to work as wrapper for icache ( when I could ensure that I could take request from cpu and send it to icache and vice versa, I'll start working on my main target).
my simple script: > ## import librarie ######### Parameters ########## > > #Memory > L1Cache = "32KiB" # same size data and instruction cache > Asso_L1 = 4 # associativity > Asso_L2 = 8 > L2Cache = "256KiB" # 8 times of L1 > L3Cache = "4096KiB" #16 times of L2 > DRAM_size = "2GiB" > ## config for interconnect netowrk > number_of_cpu = 2 > ClkFreq = "3GHz" > isa=ISA.X86 > > ################################## requires( > isa_required=ISA.X86, > kvm_required=True, > ) > > cache_hierarchy = > PrivateL1SharedL2CacheHierarchy(l1d_size=L1Cache,l1i_size=L1Cache,l2_size=L2Cache,l1d_assoc=Asso_L1,l1i_assoc=Asso_L1,l2_assoc=Asso_L2) > memory = SingleChannelDDR3_1600(DRAM_size) > processor = SimpleProcessor( cpu_type=CPUTypes.O3, > num_cores=number_of_cpu,isa=isa) > board = SimpleBoard(clk_freq=ClkFreq, processor=processor, memory=memory, > cache_hierarchy=cache_hierarchy) > #simulation setup > binary = BinaryResource('/path/to/binary') > board.set_se_binary_workload(binary) > #simulation start > simulator = Simulator(board=board) > simulator.run() In PrivateL1SharedL2CacheHierarchy(), I changed L1ICache with L1PrivateCtrl() which takes same argument as l1icache self.l1icaches = [ > L1PrivateCtrl( > icache_size=self._l1i_size, > icache_assoc=self._l1i_assoc, > icache_writeback_clean=False, > ) > for i in range(board.get_processor().get_num_cores()) > ] My L1PrivateCtrl is a library for my L1PrivateController simobject which has CacheParams icache_param as a local variable. For now, it just takes parameters for cache, assigns them in icache_param manually and instantiates cache objects with icache_param argument. Right now, I'm just trying to implement my controller object to work as an intermediary between cpu and icache. On Thu, Aug 17, 2023 at 2:37 PM Jason Lowe-Power <ja...@lowepower.com> wrote: > Hi Shaikhul, > > I think that you have somehow unset the `assoc` parameter (or set it to > None) in the cache. Can you provide us the exact script you're running, the > command line that you use to run, the information about the gem5 build > (variant used), the version of gem5 you're using, and any modifications you > have made to gem5? > > Thanks, > Jason > > On Wed, Aug 16, 2023 at 1:13 PM Khan Shaikhul Hadi via gem5-users < > gem5-users@gem5.org> wrote: > >> I have my dedicated controller module that have L1Icache as member >> function (I want to interfere with all incoming and outgoing request and >> response from cache and may modify based on some algorithm) with similler >> parameter and port structure. In PrivateL1SharedL2CacheHierarchy cache >> hierarchy, I wanted to change the L1Cache with This Controller module. When >> I run my configuration, I encountered this error: >> >> Error in unproxying param 'assoc' of board.cache_hierarchy.l1icaches0.tags >> AttributeError: Can't resolve proxy 'assoc' of type 'Int' from >> 'board.cache_hierarchy.l1icaches0.tags' >> >> Anyone have any idea how I could solve this? >> >> Note: To me it seems like, gem5 trying to create the structure of the >> system where the board trying to find the l1icaches0 directory and trying >> to get tag value from there. I could not find where it was happening. Also, >> I have found some questions where others faced the same type of error ( not >> exactly the same error) and creating a subsystem may resolve it. But I >> could not find any resources on how this subsystem structure works in gem5 >> and how to make your own subsystem. Any known resources on that? >> >> Best >> Shaikhul >> _______________________________________________ >> gem5-users mailing list -- gem5-users@gem5.org >> To unsubscribe send an email to gem5-users-le...@gem5.org >> >
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