[gem5-users] Re: Squashing Instructions after Page Table Fault

[reverent.green--- via gem5-users]

Hi Yuan,

 

thank you very much for your detailed response. My understanding of the fault handling in gem5 is getting better and better. Using debug flags, I can trace the control flow during the execution of my code.

I am currently inspecting tlb.cc in further detail, but I am still searching for the exact check for my problem.

To further specify my question:

 

During the attempt to access kernel memory, the “user/supervisor” (U/S) pagetable attribute is used to check whether this page table belongs to kernel memory or not. If I want to access the memory, it should raise the page table fault. I am looking for this specific check. My goal is, to experiment with gem5 and to customize it. Currently, the instruction is not executed when raising a Page Table Fault. In a first step, I want to change the check in order to execute the instruction although it wants to access kernel memory. So I explicitly search for this check inside this command chain during the Page Fault handling.

 

Thank you very much in advance.

 

Best regards

Robin

Gesendet: Samstag, 30. September 2023 um 01:28 Uhr
Von: "Yuan Yao via gem5-users" <gem5-users@gem5.org>
An: "The gem5 Users mailing list" <gem5-users@gem5.org>
Cc: "Yuan Yao" <yuan....@it.uu.se>
Betreff: [gem5-users] Re: Squashing Instructions after Page Table Fault

Hi Robin,

    If I understand it correctly, a Page Table Fault instruction is not squashed but *not executed*. The instruction generating a fault is marked ready to commit. Then, during the commit phase, the fault generated by the instruction is handled.

    To explain this in more detail let me I take an example of how Page Fault of a load is handled with gem5:

    1, DefaultIEW<Impl>::executeInsts() => ldstQueue.executeLoad(Inst) => inst->InitiateAcc() (dynamic inst) => staticInst->initiateAcc() (static inst) => initiateMemRead (dynamic inst again) => cpu->pushRequest() => LSQ->pushRequest() => Follow this function chain, gem5 will ultimately start the translation via the MMU module.

    2, Later after the translation is done, the page fault and the faulty instruction is marked by *translation->finish(...)* in pagetable_walker.cc (via walker:recevTimingResp, assuming that there is a page walk). The 'finish()' function is defined in the O3 pipeline components. In this case: LSQ<Impl>::SingleDataRequest::finish.

    3, Because the faulty instruction is not yet committed, DefaultIEW<Impl>::executeInsts() will check the instruction again, but this time the instruction is marked as 'TranslationCompleted'. However since <fault != NoFault>, so the instruction will be marked as executed and is forward to the commit stage (iewState->instToCommit(inst)).

    4, As the instruction moves to the head of ROB, the commitInst() function of the commit unit will call commitHead(), which further calls cpu->trap(), then fault->invoke() to handle the fault. Different faults have different invoke functions. To your question, please take a look at PageFault::invoke() at arch/x86/faults.cc. The CPU then setup the CR2 register etc and will read the ROM to launch the procedure to transfer control to OS fault handler. (The microrom is defined in romutil.py)

    5, And after the page handler is finished the fault instruction (still at the head of ROB) will be re-executed.

    The above is based on gem5 21.0.0.0 but I don't think the code changes much for the above discussions.

    Hope this helps.

    PS. Page access write is checked at the translate function in tlb.cc.

Br,

Yuan

On 9/29/23 12:28, reverent.green--- via gem5-users wrote:

A short addition. I also couldn't find a specific check for the user/supervisor Page Table Attribute anywhere.

Are there parts in the code, where specific bits are checked or does gem5 uses some other kind of implementation here?

 

 

Gesendet: Freitag, 29. September 2023 um 12:04 Uhr
Von: "reverent.green--- via gem5-users" <gem5-users@gem5.org>
An: gem5-users@gem5.org
Cc: reverent.gr...@web.de
Betreff: [gem5-users] Squashing Instructions after Page Table Fault

Hello,

 

I am currently trying to locate the code that is used to squash instructions if a Page Table Fault is triggered in the O3 CPU.

After using the PageTableWalker Debug Flags, my current guess would be gem5/src/arch/x86/pagetable_walker.cc in line 199.

Furthermore I inspected the files in the src/cpu/o3 directory, but couldn't find anything specific to squashing instructions after a fault.

 

Is my assumption correct, that the O3 CPU implementation does not handle these things on its own, but the architectural part of the implementation does it? I am missing something, feel free to point it out.

 

Thank you in advance for your help.

Kind regards

Robin

 

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