Hello everyone, I'm running some spec2017 benchmarks on gem5 and I noticed there are some dirty blocks inside the L1 instruction cache. These blocks are also shared with the L1 data cache.
So, what is a possible explanation for: 1) having dirty blocks in instruction cache and 2) having the same blocks in both L1 data and instruction caches? System configuration CPU: O3, clock=3.4GHz L1D: size=32KiB, assoc=8, latency=2 L1I: size=32KiB, assoc=8, latency=2 L2: size=128KiB, assoc=8, latency=15 No prefetchers Run for 20 million instructions I'm using private_l1_private_l2_cache_hierarchy.py Thank you, Theodoros Papavasileiou
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