Hi Theodoros, Unrelated to your question, but if you wouldn't mind sharing, how did you change the associativity of the private_l1_private_l2_cache_hierarchy.py from the default 16 to 8?
On Tue, Apr 23, 2024, 4:10 AM Theodoros Papavasiliou via gem5-users < gem5-users@gem5.org> wrote: > Hello everyone, > > I'm running some spec2017 benchmarks on gem5 and I noticed there are some > dirty blocks inside the L1 instruction cache. These blocks are also shared > with the L1 data cache. > > So, what is a possible explanation for: > 1) having dirty blocks in instruction cache and > 2) having the same blocks in both L1 data and instruction caches? > > System configuration > CPU: O3, clock=3.4GHz > L1D: size=32KiB, assoc=8, latency=2 > L1I: size=32KiB, assoc=8, latency=2 > L2: size=128KiB, assoc=8, latency=15 > No prefetchers > > Run for 20 million instructions > I'm using private_l1_private_l2_cache_hierarchy.py > > Thank you, > Theodoros Papavasileiou > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > Tianfang Guo
_______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
