Do you see any difference on other stats? There are write buffers in the caches so if you have a small benchmark that never fills them then it's possible that the write latency is hidden. You should at least see some of the stats like write buffer occupancy go up If none of the stats change, though, then something is broken.
Steve On Fri, Jun 25, 2010 at 12:41 PM, sheng qiu <[email protected]> wrote: > Hi all, > > i modified the memory access latency calculation in physical.cc: if > pkt->isWrite(), then latency = 6*lat, so write request is more expensive > than read. And i run full system simulation with timing mode. But the > results show no difference with the original unmodified result on > 'sim_ticks' under the same benchmark. I expect that the changed version > should take longer of 'sim_ticks', since the write request's latency is 6 > times more than original. Do i miss something? > > Thanks, > Sheng > > > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
