Hello all, I am attempting to create a trace of the read/write accesses when I run various benchmarks. Every time BaseDynInst::read or write is called, I save a string of bytes into an external file. As part of this information, I would really like to include just basic information about which cache level each access reaches (L1, L2, memory). I have tried a variety of approaches, from printing out something every time lsq::read or lsq::write is called, to attempting to access the cache from the BaseDynInst::read and write functions. The BaseCPU.py script refers to self.dcache and self.icache and so on; I'd really like to just call cpu->dcache.inCache(addr), but that just doesn't seem to work. Is there any way I can get the information out that I need? Thank you. Robert
_______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
