Hi, Robert, If you want to know which level the target cache is at, I can tell you a simple approach that I used.
(1) Add a member variable in the BaseCache class in both .cc and .py called cache-level. (2) Pass the cache level information to the python constructor function of L1 and L2 caches in config/example/se.py or whatever. (3) in the constructor function of C++ Caches, assign the python variable value to the C++ variable value. (4) use the cache level information in your source code. Hope it helps! Thanks, Leonard On Wed, Jul 28, 2010 at 5:09 PM, Robert England < [email protected]> wrote: > Hello all, > I am attempting to create a trace of the read/write accesses when I run > various benchmarks. Every time BaseDynInst::read or write is called, I save > a string of bytes into an external file. As part of this information, I > would really like to > include just basic information about which cache level each access reaches > (L1, L2, memory). I have tried a variety of approaches, from printing out > something every time lsq::read or lsq::write is called, to attempting to > access the cache from the > BaseDynInst::read and write functions. The BaseCPU.py script refers to > self.dcache and self.icache and so on; I'd really like to just call > cpu->dcache.inCache(addr), but that just doesn't seem to work. Is there any > way I can get the information > out that I need? Thank you. > Robert > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > -- Give our ability to our work, but our genius to our life!
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