On Thu, Oct 7, 2010 at 7:18 AM, Gabe Black <[email protected]> wrote: > Steve Reinhardt wrote: >> On Thu, Oct 7, 2010 at 2:01 AM, Glenn Ko <[email protected]> wrote: >> >>> 1. Is it because it's a 64bits and 4 bytes cannot be accessed? >>> 2. icache is working with 4 bytes because 32bit instructions are processed? >>> >> >> Yup, that's the issue. >> >> With x86 support we now support cache-line-crossing accesses, but >> that's only in the simple CPU models for now... so it might work in >> the most recent code if you leave the "-d" off your command line. >> >> Steve >> _______________________________________________ >> m5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >> > > Also accesses can only cross 1 cache line. If you have an 8 byte access > offset by 1 byte from a cache line boundary, it actually falls on 3 > cache lines and won't work. To work reliably, your block size needs to > be at least the size of the largest access that ISA performs, and in the > case of x86 I think that's 8 bytes.
Good point... but if you have an ISA that doesn't support unaligned accesses (like SPARC) you should be able to get away with a block size that's half the largest access size, right? Of course, notwithstanding the fact that it's totally unrealistic... Steve _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
