Thanks,
i have commented that line,then i got,
Global frequency set at 1000000000000 ticks per second
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7016
0: system.remote_gdb.listener: listening for remote gdb #1 on port 7017
0: system.remote_gdb.listener: listening for remote gdb #2 on port 7018
0: system.remote_gdb.listener: listening for remote gdb #3 on port 7019
Traceback (most recent call last):
File "<string>", line 1, in <module>
File "/home/rajitha/Desktop/m5/src/python/m5/main.py", line 359, in main
File "configs/splash2/run.py", line 256, in <module>
m5.instantiate(root)
File "/home/rajitha/Desktop/m5/src/python/m5/simulate.py", line 92, in
instantiate
TypeError: in method 'getCheckpoint', argument 1 of type 'std::string const
&'
can you suggest something for this?i have tried to fix it,and i am trying,
On Fri, Oct 15, 2010 at 11:48 PM, Gabe Black <[email protected]> wrote:
> I'll have to defer to Nate for an expert opinion, but I think this is a
> bug in the splash2/run.py script. The problem code is here:
>
> for cpu in cpus:
> cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1),
> L1(size = options.l1size, assoc = 4))
> cpu.mem = cpu.dcache
> # connect cpu level-1 caches to shared level-2 cache
> cpu.connectMemPorts(system.toL2bus)
>
> The addPrivateSplitL1Caches function is the following.
>
> def addPrivateSplitL1Caches(self, ic, dc):
> assert(len(self._mem_ports) < 6)
> self.icache = ic
> self.dcache = dc
> self.icache_port = ic.cpu_side
> self.dcache_port = dc.cpu_side
> self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
> if buildEnv['FULL_SYSTEM']:
> if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
> self._mem_ports += ["itb.walker.port", "dtb.walker.port"]
>
> What I think is happening is that the code in addPrivateSplitL1Caches is
> assigning the dc parameter to a member of self (the cpu), implicitly
> attaching that dcache as a child object. Then, on the second line of the
> for loop in the first blob of code (cpu.mem = cpu.dcache) the code
> attempts to assign dcache to another member of cpu, making cpu its
> parent twice. The SimObject python class gets upset about that because
> by setting up the parent of a simobject that already has one, you'll
> lose track of the original. I grepped through the code and couldn't see
> anywhere the "mem" parameter of the cpu object was actually used, so it
> might fix it to just comment that line out. I tried that, and after
> fixing your -b parameter (it should be FMM, not FFM) things seemed to work.
>
> Gabe
>
> biswabandan panda wrote:
> > hi all,
> > i have tried to run splash2 in beta 6 version
> >
> > this is my command:
> > command line: build/ALPHA_SE/m5.debug configs/splash2/run.py --rootdir
> > splash/splash2/codes -t --frequency 1GHz -n 4 --l1size 64kB --l2size
> > 256kB --l1latency 4ns --l2latency 11ns -b FFM
> >
> > these are the errors i got:
> >
> > Traceback (most recent call last):
> > File "<string>", line 1, in <module>
> > File "/home/rajitha/Desktop/m5/src/python/m5/main.py", line 359, in
> main
> > File "configs/splash2/run.py", line 197, in <module>
> > cpu.mem = cpu.dcache
> > File "/home/rajitha/Desktop/m5/src/python/m5/SimObject.py", line
> > 621, in __setattr__
> > File "/home/rajitha/Desktop/m5/src/python/m5/SimObject.py", line
> > 667, in add_child
> > RuntimeError: add_child('mem'): child 'dcache' already has parent
> > '(orphan).cpu0'
> >
> > BTW i was able to run it fine in older versions,but in beta6 these are
> > the errors.any kind of help is welcome.
> >
> > thanks
> > biswa
> > ------------------------------------------------------------------------
> >
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> > m5-users mailing list
> > [email protected]
> > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
>
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