On Tue, Nov 2, 2010 at 7:33 AM, Weixun Wang <[email protected]> wrote:
> Hi all, > > A simple question. Could any one tell me that is the miss latency (e.g., > system.cpu.dcache.overall_miss_latency) in M5 simulation output file? It is > apparently not "# number of overall miss cycles" since it has a very huge > value (e.g., 751856570000 while the cpu cycles simulated is only 783263851). > Moreover, how is this latency calculated? > The overall miss cycles is the sum of the latencies of all the misses; you divide by the number of misses to get the average miss latency. > > And I'm assuming all cache access latency, miss latency, block fill time > are incorporated in "system.cpu.numCycles", right? > I don't remember exactly what cpu.numCycles tracks vs. sim_ticks (I think it excludes idle time), but it definitely includes memory access latencies. > > Thanks. > > -- > Best Regards, > > Wang, Weixun > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
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