If that is the case, how come the total miss cycles is, for example,
751856570000 while cpu.numCycles is only 783263851? Or the former one is
in ticks?
Thanks.
Weixun
On 11/2/2010 2:54 PM, Steve Reinhardt wrote:
On Tue, Nov 2, 2010 at 7:33 AM, Weixun Wang <[email protected]
<mailto:[email protected]>> wrote:
Hi all,
A simple question. Could any one tell me that is the miss latency
(e.g., system.cpu.dcache.overall_miss_latency) in M5 simulation
output file? It is apparently not "# number of overall miss
cycles" since it has a very huge value (e.g., 751856570000 while
the cpu cycles simulated is only 783263851). Moreover, how is this
latency calculated?
The overall miss cycles is the sum of the latencies of all the misses;
you divide by the number of misses to get the average miss latency.
And I'm assuming all cache access latency, miss latency, block
fill time are incorporated in "system.cpu.numCycles", right?
I don't remember exactly what cpu.numCycles tracks vs. sim_ticks (I
think it excludes idle time), but it definitely includes memory access
latencies.
Thanks.
--
Best Regards,
Wang, Weixun
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--
Best Regards,
Wang, Weixun
Department of Computer& Information Science& Engineering
Gator College of Engineering
University of Florida
Gainesville, FL 32611
http://www.cise.ufl.edu/~wewang
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