Hi,
I have a quick question about how PowerPC out of order cpu model in SE mode.
Is the out of order model fully supported in PowerPC
The reason I am asking, is that it is not clear to me how the functional
units of the PowerPC architecture are assigned their latencies. I found that
the file src\cpu\o3\FuncUnitConfig.py contains the functional unit
configuration and which instructions the units handle. For example the
FP_MultDiv unit handles the FloatMult instructions among other instructions
class FP_MultDiv(FUDesc):
opList = [ OpDesc(opClass='FloatMult', opLat=4),
OpDesc(opClass='FloatDiv', opLat=12, issueLat=12),
OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ]
count = 2
However when I grep the source folder for FloatMult, I find that only the
alpha architecture instruction decoder assigns the Opclass types. So how is
the simulation of powerpc functional units done?
[same...@cyclades-master m5]$ grep -r FloatMult ./src
./src/arch/alpha/isa/decoder.isa: 0x02: muls({{ Fc =
Fa * Fb; }}, FloatMultOp);
./src/arch/alpha/isa/decoder.isa: 0x02: muls({{ Fc.sf
= Fa.sf * Fb.sf; }}, FloatMultOp);
./src/arch/alpha/isa/decoder.isa: 0x22: mult({{ Fc =
Fa * Fb; }}, FloatMultOp);
./src/cpu/FuncUnit.py: 'FloatCmp', 'FloatCvt', 'FloatMult',
'FloatDiv', 'FloatSqrt',
./src/cpu/o3/FuncUnitConfig.py: opList = [ OpDesc(opClass='FloatMult',
opLat=4),
./src/cpu/op_class.hh:const OpClass FloatMultOp = Enums::FloatMult;
Thanks for clarifying.
Sameh
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