No, that's not true... the out-of-order scheduling will happen regardless of functional unit assignment. I'm guessing that what happens is that all instructions get assigned to some default functional unit type (probably integer ALU), and I'm pretty sure the default O3 model has multiple integer ALUs, so I'm pretty confident you'd be getting out-of-order behavior. It's just not accurately reflecting the resource constraints of how instructions would map to different units.
Steve On Thu, Dec 2, 2010 at 10:57 AM, Sameh Galal <[email protected]> wrote: > Thanks for the info. If that's true, then none of the instructions are > assigned to any functional unit, i assume the machine just behaves like an > in-order machine which is not what the O3 cpu model was built for .. > > Sameh > > > On Wed, Dec 1, 2010 at 10:58 PM, Gabe Black <[email protected]> wrote: > >> It should work functionally. It's quite possible classifying >> instructions like that in Power was left for after things worked >> functionally and never revisited. This is almost certainly the case for >> some of the other ISAs. You can attempt to change the isa description >> yourself so that the right op class is used. Because the description is >> built in a custom language it can be tricky to figure out what's going >> on, but if Power is structured similar to Alpha then the op class >> setting code may be pretty easy to port if it isn't in there already. >> When you configure the functional unit in O3, don't change the file in >> src/ since those files only set the default value. You'll want to change >> the value in the CPU you're instantiating in a configuration script. >> That way you won't have to recompile M5 to try a new value. >> >> Gabe >> >> Sameh Galal wrote: >> > Hi, >> > I have a quick question about how PowerPC out of order cpu model in SE >> > mode. Is the out of order model fully supported in PowerPC >> > >> > The reason I am asking, is that it is not clear to me how the >> > functional units of the PowerPC architecture are assigned their >> > latencies. I found that the file src\cpu\o3\FuncUnitConfig.py contains >> > the functional unit configuration and which instructions the units >> > handle. For example the FP_MultDiv unit handles the FloatMult >> > instructions among other instructions >> > >> > class FP_MultDiv(FUDesc): >> > opList = [ OpDesc(opClass='FloatMult', opLat=4), >> > OpDesc(opClass='FloatDiv', opLat=12, issueLat=12), >> > OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ] >> > count = 2 >> > >> > However when I grep the source folder for FloatMult, I find that only >> > the alpha architecture instruction decoder assigns the Opclass types. >> > So how is the simulation of powerpc functional units done? >> > >> > [same...@cyclades-master m5]$ grep -r FloatMult ./src >> > ./src/arch/alpha/isa/decoder.isa: 0x02: muls({{ >> > Fc = Fa * Fb; }}, FloatMultOp); >> > ./src/arch/alpha/isa/decoder.isa: 0x02: muls({{ >> > Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp); >> > ./src/arch/alpha/isa/decoder.isa: 0x22: mult({{ >> > Fc = Fa * Fb; }}, FloatMultOp); >> > ./src/cpu/FuncUnit.py: 'FloatCmp', 'FloatCvt', 'FloatMult', >> > 'FloatDiv', 'FloatSqrt', >> > ./src/cpu/o3/FuncUnitConfig.py: opList = [ >> > OpDesc(opClass='FloatMult', opLat=4), >> > ./src/cpu/op_class.hh:const OpClass FloatMultOp = Enums::FloatMult; >> > >> > Thanks for clarifying. >> > Sameh >> > ------------------------------------------------------------------------ >> > >> > _______________________________________________ >> > m5-users mailing list >> > [email protected] >> > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >> >> _______________________________________________ >> m5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >> > > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
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