Hi, I am running the stable version of M5 and I am using SimpleAtomicCPU for my simulations. I conducted 2 identical simulations with the only difference being that in the first simulation the L2 cache is 10 ways 1280kB and in the second simulation simulation the L2 cache is 12 ways 1536kB. In stats.txt, I see that system.l2.overall_accesses of the two runs are not the same. Shouldn't they be the same? Why would the size of L2 alone make a difference in the number of L2 accesses? I am attaching the output config files. Again, the two simulations only differ in the size and associativity of the L2 as can be seen through the config files. Thanks, Steve
config.ini
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