Since you're running a full-system workload, small changes in timing can change the execution path due to interrupts occurring in different places relative to the instruction stream, etc. I'm a little surprised it makes a difference with SimpleAtomicCPU, since the memory-system behavior shouldn't influence CPU timing, but there could be some small ways in which it leaks through.
If you really want to know what's going on, use the util/tracediff script to compare trace outputs from the two runs to see where they diverge (see the comments in the script for more details). Please let us know what you find. Steve On Mon, Dec 6, 2010 at 2:25 PM, Stevenson Jian <[email protected]>wrote: > Hi, > I am running the stable version of M5 and I am using SimpleAtomicCPU for my > simulations. I conducted 2 identical simulations with the only difference > being that in the first simulation the L2 cache is 10 ways 1280kB and in the > second simulation simulation the L2 cache is 12 ways 1536kB. In stats.txt, I > see that system.l2.overall_accesses of the two runs are not the same. > Shouldn't they be the same? Why would the size of L2 alone make a difference > in the number of L2 accesses? > I am attaching the output config files. Again, the two simulations only > differ in the size and associativity of the L2 as can be seen through the > config files. > Thanks, > Steve > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
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