See http://m5sim.org/wiki/index.php/Memory_System#Access_Types. Functional accesses get instantaneously broadcast through the whole system, which is why every cache reports that it is processing the access at the same tick.
Steve On Mon, Jan 24, 2011 at 1:33 AM, biswabandan panda <[email protected]>wrote: > in the trace file of cache memory i got something like this > > > 243399000: system.l2: functional WriteReq d1c40 > 243399000: system.cpu0.dcache: functional WriteReq d1c80 > 243399000: system.cpu0.icache: functional WriteReq d1c80 > 243399000: system.cpu1.icache: functional WriteReq d1c80 > 243399000: system.cpu1.dcache: functional WriteReq d1c80 > > all are in same clock tick with same address, what does it mean? > > > -- > > *thanks®ards > * > *BISWABANDAN PANDA* > *M.S.(RESEARCH SCHOLAR)* > *RISE LAB* > *IIT MADRAS* > > http://www.cse.iitm.ac.in/~biswa/ <http://www.cse.iitm.ac.in/%7Ebiswa/> > > "Happy new Year 2011" > > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
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