Hi Rick, Did you figure out what was the problem? I am having the same problem here. Moreover, I also had another problem: When I resume from a checkpoint: ./build/ALPHA_SE/m5.opt configs/example/se.py --bench bzip2 --checkpoint-restore=0 --simpoint
I have this error: Exiting @ cycle 1100301000 because halt instruction encountered. Btw, I created the checkpoint by using: ./build/ALPHA_SE/m5.opt configs/example/se.py --bench bzip2 --take-checkpoint=0 --simpoint Could anyone give some suggestions? Thanks! -Sheng On Mon, Jan 24, 2011 at 8:32 PM, Steve Reinhardt <[email protected]> wrote: > That is pretty freaky... you get the warnings by default, I think, but you > can try the 'Config' traceflag. Feel free to add more DPRINTFs if that > doesn't help. The unserialization is driven by the objects, so the question > is why the PageTable in the Process object unserializes correctly in one > case but not in the other. You could try putting a breakpoint in > PageTable::unserialize and running under gdb to see what's going on. > > Steve > > On Mon, Jan 24, 2011 at 5:00 PM, Richard Strong <[email protected]>wrote: > >> Hi all, >> >> I tried resuming several spec 2006 benchmarks from a checkpoint in >> ALPHA_SE but I get; >> >> panic: Tried to execute unmapped address 0x<some address greater than >> zero>. >> >> The system works fine if I use a single core, with 1 dcache and 1 icache. >> However, if I add an l2 cache to this system, I get the panic. A closer >> looks indicates that if I specify the l2cache option for se.py, the portion >> of the code that unserializes the page table entries never executes so the >> pagetable is empty. However, if I do not specify the l2cache option, then >> the the page table entries are unserialized just fine. Is it possible that >> the addition of a l2cache or a l2bus is causing the unserialize code to >> fail? Is there a flag option for trace-flags that will dump out all the >> warning and info during the unserialize portion of execution? >> >> Thanks in advance, >> Rick >> >> >> >> _______________________________________________ >> m5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >> > > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >
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