Re: [m5-users] more than one reuest in one tick

Mon, 07 Feb 2011 19:54:02 -0800 

i think its because of out of order superscalar processor

On Tue, Feb 8, 2011 at 9:12 AM, biswabandan panda <[email protected]>wrote:

> Hi all,
>                in the trace of cache i got something like this, i wonder in
> one tick how so many requests possible?
>  114660500: system.cpu0.dcache: WriteReq  set: 122 block: 802432   hit
> 114660500: system.cpu0.dcache: WriteReq  set: 122 block: 802432   hit
> 114660500: system.cpu0.dcache: WriteReq  set: 122 block: 802432   hit
> 114660500: system.cpu0.dcache: WriteReq  set: 122 block: 802432   hit
>
>
>
>
> --
>
> *thanks&regards
> *
> *BISWABANDAN PANDA*
> *M.S.(RESEARCH SCHOLAR)*
> *RISE LAB*
> *IIT MADRAS*
>
> http://www.cse.iitm.ac.in/~biswa/
>
>
>


-- 

*thanks&regards
*
*BISWABANDAN PANDA*
*M.S.(RESEARCH SCHOLAR)*
*RISE LAB*
*IIT MADRAS*

http://www.cse.iitm.ac.in/~biswa/

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