Sylvere,
Your instantiation of the rom is wrong , try the attached version of
the testbench.
You have to provide the model with two files .
Regards
Michel Agoyan
(EMSE , CMP)
Sylvere Teissier a écrit :
Hello,
I found a bug in GHDL with Spansion flash model (segfault)
It seems that there is a weird problem at elaboration:
(gdb) run
Starting program: /home/steissier/temp/test_spansion/testbench
--stop-time=100ns
Program received signal SIGSEGV, Segmentation fault.
0x403c975d in memmove () from /lib/i686/cmov/libc.so.6
(gdb) where
#0 0x403c975d in memmove () from /lib/i686/cmov/libc.so.6
#1 0x080d3efb in __ghdl_memcpy ()
#2 0x08053a2f in work__testbench__ARCH__tb__rom__ELAB
(INSTANCE=0x9fe2428)
at testbench.vhd:16
#3 0x080551b9 in work__testbench__ARCH__tb__ELAB (INSTANCE=0x9fe2428)
at testbench.vhd:13
#4 0x0804a524 in __ghdl_ELABORATE ()
#5 0x080e8068 in grt__main__run ()
#6 0x080e66fd in ghdl_main ()
#7 0x080e2e72 in main ()
Makefile and sources are in attachment
------------------------------------------------------------------------
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library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_timing.all;
use IEEE.VITAL_primitives.all;
use STD.textio.all;
library FMF;
use FMF.gen_utils.all;
use FMF.conversions.all;
entity testbench is
end entity;
architecture tb of testbench is
signal address : std_logic_vector(17 downto
0) := (others => '1');
signal data : std_logic_vector(15 downto
0) := (others => 'Z');
signal ce_n, oe_n, we_n, reset_n, byte_n, ready : std_logic
:= '0';
component s29al004d
generic (
tipd_A0 : VitalDelayType01;
tipd_A1 : VitalDelayType01;
tipd_A2 : VitalDelayType01;
tipd_A3 : VitalDelayType01;
tipd_A4 : VitalDelayType01;
tipd_A5 : VitalDelayType01;
tipd_A6 : VitalDelayType01;
tipd_A7 : VitalDelayType01;
tipd_A8 : VitalDelayType01;
tipd_A9 : VitalDelayType01;
tipd_A10 : VitalDelayType01;
tipd_A11 : VitalDelayType01;
tipd_A12 : VitalDelayType01;
tipd_A13 : VitalDelayType01;
tipd_A14 : VitalDelayType01;
tipd_A15 : VitalDelayType01;
tipd_A16 : VitalDelayType01;
tipd_A17 : VitalDelayType01;
tipd_DQ0 : VitalDelayType01;
tipd_DQ1 : VitalDelayType01;
tipd_DQ2 : VitalDelayType01;
tipd_DQ3 : VitalDelayType01;
tipd_DQ4 : VitalDelayType01;
tipd_DQ5 : VitalDelayType01;
tipd_DQ6 : VitalDelayType01;
tipd_DQ7 : VitalDelayType01;
tipd_DQ8 : VitalDelayType01;
tipd_DQ9 : VitalDelayType01;
tipd_DQ10 : VitalDelayType01;
tipd_DQ11 : VitalDelayType01;
tipd_DQ12 : VitalDelayType01;
tipd_DQ13 : VitalDelayType01;
tipd_DQ14 : VitalDelayType01;
tipd_DQ15 : VitalDelayType01;
tipd_CENeg : VitalDelayType01;
tipd_OENeg : VitalDelayType01;
tipd_WENeg : VitalDelayType01;
tipd_RESETNeg : VitalDelayType01;
tipd_BYTENeg : VitalDelayType01;
tpd_RESETNeg_DQ0 : VitalDelayType01Z;
tpd_A0_DQ0 : VitalDelayType01;
tpd_CENeg_DQ0 : VitalDelayType01Z;
tpd_OENeg_DQ0 : VitalDelayType01Z;
tpd_WENeg_RY : VitalDelayType01;
tpd_BYTENeg_DQ15 : VitalDelayType01Z;
tsetup_A0_CENeg : VitalDelayType;
tsetup_DQ0_CENeg : VitalDelayType;
tsetup_OENeg_WENeg : VitalDelayType;
tsetup_CENeg_WENeg : VitalDelayType;
thold_A0_CENeg : VitalDelayType;
thold_DQ0_CENeg : VitalDelayType;
thold_OENeg_WENeg : VitalDelayType;
thold_CENeg_WENeg : VitalDelayType;
thold_CENeg_RESETNeg : VitalDelayType;
thold_BYTENeg_CENeg : VitalDelayType;
tpw_RESETNeg_negedge : VitalDelayType;
tpw_WENeg_negedge : VitalDelayType;
tpw_WENeg_posedge : VitalDelayType;
tpw_A0_negedge : VitalDelayType;
tdevice_POB : VitalDelayType;
tdevice_POW : VitalDelayType;
tdevice_SEO : VitalDelayType;
tdevice_HANG : VitalDelayType;
tdevice_START_T1 : VitalDelayType;
tdevice_CTMOUT : VitalDelayType;
tdevice_READY : VitalDelayType;
InstancePath : string;
TimingChecksOn : boolean;
MsgOn : boolean;
XOn : boolean;
mem_file_name : string;
prot_file_name : string;
UserPreload : boolean;
LongTimming : boolean;
TimingModel : string);
port (
A17 : in std_ulogic := 'U';
A16 : in std_ulogic := 'U';
A15 : in std_ulogic := 'U';
A14 : in std_ulogic := 'U';
A13 : in std_ulogic := 'U';
A12 : in std_ulogic := 'U';
A11 : in std_ulogic := 'U';
A10 : in std_ulogic := 'U';
A9 : in std_ulogic := 'U';
A8 : in std_ulogic := 'U';
A7 : in std_ulogic := 'U';
A6 : in std_ulogic := 'U';
A5 : in std_ulogic := 'U';
A4 : in std_ulogic := 'U';
A3 : in std_ulogic := 'U';
A2 : in std_ulogic := 'U';
A1 : in std_ulogic := 'U';
A0 : in std_ulogic := 'U';
DQ15 : inout std_ulogic := 'U';
DQ14 : inout std_ulogic := 'U';
DQ13 : inout std_ulogic := 'U';
DQ12 : inout std_ulogic := 'U';
DQ11 : inout std_ulogic := 'U';
DQ10 : inout std_ulogic := 'U';
DQ9 : inout std_ulogic := 'U';
DQ8 : inout std_ulogic := 'U';
DQ7 : inout std_ulogic := 'U';
DQ6 : inout std_ulogic := 'U';
DQ5 : inout std_ulogic := 'U';
DQ4 : inout std_ulogic := 'U';
DQ3 : inout std_ulogic := 'U';
DQ2 : inout std_ulogic := 'U';
DQ1 : inout std_ulogic := 'U';
DQ0 : inout std_ulogic := 'U';
CENeg : in std_ulogic := 'U';
OENeg : in std_ulogic := 'U';
WENeg : in std_ulogic := 'U';
RESETNeg : in std_ulogic := 'U';
BYTENeg : in std_ulogic := 'U';
RY : out std_ulogic := 'U');
end component;
begin
s29al004d_1 : s29al004d
generic map (
tipd_A0 => VitalZeroDelay01,
tipd_A1 => VitalZeroDelay01,
tipd_A2 => VitalZeroDelay01,
tipd_A3 => VitalZeroDelay01,
tipd_A4 => VitalZeroDelay01,
tipd_A5 => VitalZeroDelay01,
tipd_A6 => VitalZeroDelay01,
tipd_A7 => VitalZeroDelay01,
tipd_A8 => VitalZeroDelay01,
tipd_A9 => VitalZeroDelay01,
tipd_A10 => VitalZeroDelay01,
tipd_A11 => VitalZeroDelay01,
tipd_A12 => VitalZeroDelay01,
tipd_A13 => VitalZeroDelay01,
tipd_A14 => VitalZeroDelay01,
tipd_A15 => VitalZeroDelay01,
tipd_A16 => VitalZeroDelay01,
tipd_A17 => VitalZeroDelay01,
tipd_DQ0 => VitalZeroDelay01,
tipd_DQ1 => VitalZeroDelay01,
tipd_DQ2 => VitalZeroDelay01,
tipd_DQ3 => VitalZeroDelay01,
tipd_DQ4 => VitalZeroDelay01,
tipd_DQ5 => VitalZeroDelay01,
tipd_DQ6 => VitalZeroDelay01,
tipd_DQ7 => VitalZeroDelay01,
tipd_DQ8 => VitalZeroDelay01,
tipd_DQ9 => VitalZeroDelay01,
tipd_DQ10 => VitalZeroDelay01,
tipd_DQ11 => VitalZeroDelay01,
tipd_DQ12 => VitalZeroDelay01,
tipd_DQ13 => VitalZeroDelay01,
tipd_DQ14 => VitalZeroDelay01,
tipd_DQ15 => VitalZeroDelay01,
tipd_CENeg => VitalZeroDelay01,
tipd_OENeg => VitalZeroDelay01,
tipd_WENeg => VitalZeroDelay01,
tipd_RESETNeg => VitalZeroDelay01,
tipd_BYTENeg => VitalZeroDelay01,
tpd_RESETNeg_DQ0 => UnitDelay01Z,
tpd_A0_DQ0 => UnitDelay01,
tpd_CENeg_DQ0 => UnitDelay01Z,
tpd_OENeg_DQ0 => UnitDelay01Z,
tpd_WENeg_RY => UnitDelay01,
tpd_BYTENeg_DQ15 => UnitDelay01Z,
tsetup_A0_CENeg => UnitDelay,
tsetup_DQ0_CENeg => UnitDelay,
tsetup_OENeg_WENeg => UnitDelay,
tsetup_CENeg_WENeg => UnitDelay,
thold_A0_CENeg => UnitDelay,
thold_DQ0_CENeg => UnitDelay,
thold_OENeg_WENeg => UnitDelay,
thold_CENeg_WENeg => UnitDelay,
thold_CENeg_RESETNeg => UnitDelay,
thold_BYTENeg_CENeg => UnitDelay,
tpw_RESETNeg_negedge => UnitDelay,
tpw_WENeg_negedge => UnitDelay,
tpw_WENeg_posedge => UnitDelay,
tpw_A0_negedge => UnitDelay,
tdevice_POB => 5 us,
tdevice_POW => 7 us,
tdevice_SEO => 700 ms,
tdevice_HANG => 400 ms,
tdevice_START_T1 => 20 us,
tdevice_CTMOUT => 50 us,
tdevice_READY => 20 us,
InstancePath => DefaultInstancePath,
TimingChecksOn => DefaultTimingChecks,
MsgOn => DefaultMsgOn,
XOn => DefaultXon,
mem_file_name => "s29al004d.mem",
prot_file_name => "s29al004d_prot.mem",
UserPreload => false,
LongTimming => true,
TimingModel => "S29AL004D55TAI01")
port map(
A17 => address(17),
A16 => address(16),
A15 => address(15),
A14 => address(14),
A13 => address(13),
A12 => address(12),
A11 => address(11),
A10 => address(10),
A9 => address(9),
A8 => address(8),
A7 => address(7),
A6 => address(6),
A5 => address(5),
A4 => address(4),
A3 => address(3),
A2 => address(2),
A1 => address(1),
A0 => address(0),
DQ15 => data(15),
DQ14 => data(14),
DQ13 => data(13),
DQ12 => data(12),
DQ11 => data(11),
DQ10 => data(10),
DQ9 => data(9),
DQ8 => data(8),
DQ7 => data(7),
DQ6 => data(6),
DQ5 => data(5),
DQ4 => data(4),
DQ3 => data(3),
DQ2 => data(2),
DQ1 => data(1),
DQ0 => data(0),
CENeg => ce_n,
OENeg => oe_n,
WENeg => we_n,
RESETNeg => reset_n,
BYTENeg => byte_n,
RY => ready
);
test : process
begin
address <= "00" & x"0004";
data <= (others => 'Z');
ce_n <= '0';
we_n <= '1';
oe_n <= '0';
byte_n <= '1';
reset_n <= '1';
wait for 200 ns;
address <= "00" & x"0014";
data <= (others => 'Z');
wait for 200 ns;
wait;
end process;
end architecture;
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