Quoting Fabien Marteau <[email protected]>: > Hy, > > I managed to compile Xilinx library unisim and simprim following this > instruction mail : > https://mail.gna.org/public/ghdl-discuss/2007-10/msg00016.html > > That work well to simulate Bloc of ram using unisim in behavioural > simulation, but I have lot of warning and error when I simulate post place & > route simulation model (myproject_timesim.vhd) :
Most of these errors can be ignored. > And when I run simulation I've a simulation error : > >simu/top_test_latency_logger_tb:error: NULL access dereferenced > >simu/top_test_latency_logger_tb:error: simulation failed > >make: *** [ghdl-run] Erreur 1 > > Does somebody has already experimented post place and route simulation ? Yes I have already tried. If you can send a reproducer I could have a look. Tristan. _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
