Fabien Marteau wrote:
>...
> Does somebody has already experimented post place and route simulation ?
Hi Fabien,
yes, I'm using ghdl for 'post synthesis' as well as 'post place and route'
models, the respective netgen commands are (taken from my master Makefile)
netgen -sim -intstyle xflow -ofmt vhdl -w $*.ngc
netgen -ofmt vhdl -sim -w -intstyle xflow -pcf $*.pcf $*.ncd $*_tsim.vhd
The unisim based post-xst models are still quite compact and reasonable fast,
while the simprim based post-par models are quite large and slow due to all
the delay modeling.
Because post-par models tend to have very many processes it's sometimes
necessary to give a few hints on stack sizes
1. allow linux to handle many mmaps
echo 131072 > /proc/sys/vm/max_map_count
2. start ghdl with --stack-max-size=16384
This way a model with
Number of processes: 43095
Number of sensitized processes: 11866
Number of mmaps: 62479
virtual size: 526m
finally worked, albeit at a quite modest speed....
In one case I had a post-par model which just hung, the post-xst or original
vhdl did just fine, the design worked in FPGA. Unclear why, the issue
disappeared a few ISE versions later.
What never worked for me is sdf annotation. I can run a post-par model without
--sdf, but with a '--sdf=uut=<design>.sdf' I get an error, apparently the sdf
file format isn't compatible with what ghdl expects. I posted that a week ago.
I hope that helps a bit.
With best regards, Walter
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