Hi Tristan! Tristan Gingold escribió: > I did a lot of profiling using a large design (leon). Hmmm ... LEON isn't a good example of normal VHDL coding. Gaisler used a special technique to code LEON, this technique is very different to regular VHDL coding. A paper (included in a chapter of LEON docs) explains it. Is something like this: blocks get in/out records containing all the I/O. One process determines the next state from the current and the I/O. Another process transfers the next state to the current and sets the outputs. According to Gaisler it allows for a much higher abstraction. We tried to apply this technique with mixed results, usually involving slower simulation as the portions recoded like this increased.
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