Hallo Tirstan,
I have written a reproducer. This is also simplier for you.
The concept is a continuesly calculation.
The math is normaly in the function step and is an iterative operation.
The next step depends from a former result. I have reduce the math in
this function.
The math is al little more complex at me.
ghdl -a -Wa,--32 co_tb.vhd
r...@x1-6-00-1d-92-05-7d-7a:~/fpga/VHDL/ghdl/co_dummy> ghdl -a -Wa,--32
co_dummy.vhd
r...@x1-6-00-1d-92-05-7d-7a:~/fpga/VHDL/ghdl/co_dummy> ghdl -e -Wa,--32
-Wl,-m32 co_tb
r...@x1-6-00-1d-92-05-7d-7a:~/fpga/VHDL/ghdl/co_dummy> ghdl -r co_tb
../../../src/ieee/numeric_std-body.v93:1710:7:@45095ns:(assertion
warning): NUMERIC_STD."=": metavalue detected, returning FALSE
../../../src/ieee/numeric_std-body.v93:1710:7:@45095ns:(assertion
warning): NUMERIC_STD."=": metavalue detected, returning FALSE
../../../src/ieee/numeric_std-body.v93:1710:7:@45095ns:(assertion
warning): NUMERIC_STD."=": metavalue detected, returning FALSE
../../../src/ieee/numeric_std-body.v93:1710:7:@45095ns:(assertion
warning): NUMERIC_STD."=": metavalue detected, returning FALSE
../../../src/ieee/numeric_std-body.v93:1710:7:@45095ns:(assertion
warning): NUMERIC_STD."=": metavalue detected, returning FALSE
../../../src/ieee/numeric_std-body.v93:1710:7:@45095ns:(assertion
warning): NUMERIC_STD."=": metavalue detected, returning FALSE
../../../src/ieee/numeric_std-body.v93:1710:7:@45095ns:(assertion
warning): NUMERIC_STD."=": metavalue detected, returning FALSE
../../../src/ieee/numeric_std-body.v93:1710:7:@45105ns:(assertion
warning): NUMERIC_STD."=": metavalue detected, returning FALSE
>> I take a larger stack.
>>
>> ghdl -r co_tb --stack-size=1000000000
>> ../../../src/ieee/numeric_std-body.v93:1278:7:@10ns:(assertion warning):
>> NUMERIC_STD."<": metavalue detected, returning FALSE
>> ./co_tb:error: invalid memory access (dangling accesses or stack size
>> too small)
>> ghdl: exec error
>>
>>
>>
>> I have in a process like this.
>>
>> a,b :type_record;
>>
>> process(clk)
>> begin
>> if( clk'EVENT and clk='1') then
>> a<=b;
>> end process;
>>
>
> Note: if you want me to investigate this issue I need either your design
> or a reproducer. This could be a bug within ghdl.
>
> Tristan.
>
> _______________________________________________
> Ghdl-discuss mailing list
> [email protected]
> https://mail.gna.org/listinfo/ghdl-discuss
>
>
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity co_dummy is
generic (interations :integer :=10);
PORT( angle : IN unsigned (7 DOWNTO 0);
clk: In std_logic;
signal_a : OUT unsigned(7 DOWNTO 0);
signal_b : OUT unsigned(7 DOWNTO 0)
);
end co_dummy;
architecture Behavioral of co_dummy is
type vec is record
reg_a: unsigned (7 downto 0);
reg_b: unsigned (7 downto 0);
phase: unsigned (7 downto 0);
end record;
function step(i:integer; step: vec) return vec is
variable temp : vec;
begin
if((step.phase)=3) then
temp.reg_a:=step.reg_b;
temp.reg_b:=step.reg_a;
--temp.phase:=step.phase+value;
temp.phase:=step.phase+1;
else
temp.reg_a:=step.reg_a+1;
temp.reg_b:=step.reg_b+4;
--temp.phase:=step.phase+value;
temp.phase:=step.phase+1;
end if;
return temp;
end step;
type co_pipe is array (0 to interations) of vec;
signal pipe :co_pipe;
begin
init: PROCESS(clk)
begin
if( clk'EVENT and clk='1') then
if (angle(7 downto 6) ="00") THEN --Quadrant I
pipe(0).phase <= to_unsigned(0,8);
pipe(0).reg_a<=to_unsigned(0,8);
pipe(0).reg_b<=to_unsigned(0,8);
end if;
if (angle(7 downto 6) = "01") THEN --Quadrant II
pipe(0).phase<=to_unsigned(0,8);
pipe(0).reg_a <=to_unsigned(20,8);
pipe(0).reg_b <=to_unsigned(0,8);
end if;
if (angle(7 downto 6) ="10") THEN --Quadrant III
pipe(0).phase<=to_unsigned(0,8);
pipe(0).reg_a<=to_unsigned(0,8);
pipe(0).reg_b<=to_unsigned(20,8);
end if;
if (angle(7 downto 6) = "11") THEN --Quadrant IV
pipe(0).phase<=to_unsigned(0,8);
pipe(0).reg_a<=to_unsigned(0,8);
pipe(0).reg_b<=to_unsigned(0,8);
end if;
end if;
end process;
PROCESS(clk)
begin
if( clk'EVENT and clk='1') then
for s in interations downto 1 loop
pipe(s)<=step(s-1,pipe(s-1));
end loop;
end if;
end process;
pipe_out: process(clk)
begin
if( clk'EVENT and clk='1') then
signal_a<=pipe(interations).reg_a;
signal_b<=pipe(interations).reg_b;
end if;
end process;
end Behavioral;
-------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY co_tb IS
END co_tb;
ARCHITECTURE behavior OF co_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT co_dummy
PORT(
angle : IN unsigned(7 downto 0);
clk : IN std_logic;
signal_a : OUT unsigned(7 downto 0);
signal_b : OUT unsigned(7 downto 0)
);
END COMPONENT;
--Inputs
signal angle : unsigned(7 downto 0) := (others => '0');
signal clk : std_logic := '0';
--Outputs
signal signal_a : unsigned(7 downto 0);
signal signal_b : unsigned(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns; --100Mhz
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: co_dummy PORT MAP (
angle => angle,
clk => clk,
signal_a => signal_a,
signal_b => signal_b
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
process (clk)
begin
if( clk'EVENT and clk='1') then
angle<=angle+1;
end if;
end process;
END;
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