Hi, I've just started to use gHDL. I have a design with local variables inside a process block. After running a simulation these signals are not in the VCD file. How can I get gHDL to dump all signals / variables in the design?
Thanks, Kelvin Gardiner _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
