Its always like that. Variables are not visible in simulation. Kind of sucks but you have to make it a signal if you want to see it in sim.
Greg On Tue, Nov 17, 2009 at 6:53 AM, Kelvin Gardiner <[email protected]> wrote: > Hi, > > I've just started to use gHDL. I have a design with local variables > inside a process block. After running a simulation these signals are not > in the VCD file. How can I get gHDL to dump all signals / variables in > the design? > > Thanks, > Kelvin Gardiner > > _______________________________________________ > Ghdl-discuss mailing list > [email protected] > https://mail.gna.org/listinfo/ghdl-discuss >
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