In pondering how one might approach a mixed-language simulation with FOSS tools, I recently noticed that Icarus can compile the verilog input and export it to VHDL. Has anyone tried to bring this translated VHDL from verilog into a GHDL simulation? How well would this work? Is it usable, or more of an automated beginning to a translation which will require manual effort as well to make that VHDL usable?
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