Learning a bit more, I decided to change the lines:
s1 <= '1';
s1 <= '0' after CLK_PER*2;
to:
s1 <= '1', '0' after CLK_PER*2;
and also to
s1 <= '1';
s1 <= transport '0' after CLK_PER*2;
None of the new two options do what I expect. Are those also wrong?
Thank you,
Lluís.
2010/3/25 Lluís Batlle <[email protected]>:
> Hello,
>
> I don't have any other vhdl simulator at hand other than ghdl. Could
> you take a look at the example code I attach?
>
> I think it should show the signal 's1' enabled for two clock periods,
> but 's1' never gets the value '1'.
>
> Is there a problem in ghdl, or I understand the 'after' keyword wrong?
>
> Thank you,
> Lluís.
>
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