Is your code within a process? If it is then the first assignment is being overridden by the second: in a process only the last assignment to a signal takes effect.
Probably what you want is: s <= '1'; wait for 2* CLK_PER; s <= '0'; (just bear in mind that your process can't have a sensitivity list if it has a wait statement in it, although you can get round this with "wait on ..." at the start. On 25 March 2010 08:37, Lluís Batlle <[email protected]> wrote: > Learning a bit more, I decided to change the lines: > s1 <= '1'; > s1 <= '0' after CLK_PER*2; > > to: > s1 <= '1', '0' after CLK_PER*2; > and also to > s1 <= '1'; > s1 <= transport '0' after CLK_PER*2; > > None of the new two options do what I expect. Are those also wrong? > > Thank you, > Lluís. > > 2010/3/25 Lluís Batlle <[email protected]>: > > Hello, > > > > I don't have any other vhdl simulator at hand other than ghdl. Could > > you take a look at the example code I attach? > > > > I think it should show the signal 's1' enabled for two clock periods, > > but 's1' never gets the value '1'. > > > > Is there a problem in ghdl, or I understand the 'after' keyword wrong? > > > > Thank you, > > Lluís. > > > > _______________________________________________ > Ghdl-discuss mailing list > [email protected] > https://mail.gna.org/listinfo/ghdl-discuss >
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