On 27/06/11 4:57 PM, David G. Koontz wrote:
> Now for the kicker. The original ghdl_bug.vhdl code should not work,
> because it is modulo 2047. val is incremented by one, becomes now 2047
> (2**11-1) and is immediately reset to 0 before it can be used. The
> available outputs are 0 to 2046.
>
> Pre increment and the test value should be 2**11 (2048). Fix it (in
> ghdl_bug8.vhdl) and it works just fine.
>
> ghdl_bug.vhdl (your original test case) runs val modulo 2047, while
> ghdl_bug7.vhdl and ghdl_bug8.vhdl both operate val modulo 2048.
>
> Your test case is defective.
>
This revisits my original comment on a numeric_std version of num not
producing assertion reports.
The conversion of clk to std_logic and num to numeric_std (ghdl_bug3.vhdl)
generates no errors.
The reason for the clk to std_logic lack of assertion errors is readily
apparent. See ghdl_bug9.vhdl wherein the comparison between val and
to_integer(num) occurs has it's sense inverted which should generate report
statements for all occurrences not previously reported.
In this case neither ghdl_bug3.vhdl nor ghdl_bug9.vhdl generate report
statements. The reason for this is a lack of useful events on the clk
signal whose default value is 'U'. NOT 'U' doesn't produce a useful value.
Converting just num to numeric_std through a precarious collection of use
clauses (ghdl_bug11.vhdl) preserving clk as type bit still produces errors:
Macbook: ghdl -r ghdl_bug bug --stop-time=40960ns
ghdl_bug11.vhdl:38:5:@40930001ps:(assertion error): expected = 0 actual = 2047
ghdl_bug11.vhdl:38:5:@40950001ps:(assertion error): expected = 1 actual = 0
ghdl:info: simulation stopped by --stop-time
and for the second precession:
Macbook: ghdl -r ghdl_bug bug --stop-time=81920ns
(tail -6)
ghdl_bug11.vhdl:38:5:@81830001ps:(assertion error): expected = 2045 actual =
2044
ghdl_bug11.vhdl:38:5:@81850001ps:(assertion error): expected = 2046 actual =
2045
ghdl_bug11.vhdl:38:5:@81870001ps:(assertion error): expected = 0 actual = 2046
ghdl_bug11.vhdl:38:5:@81890001ps:(assertion error): expected = 1 actual = 2047
ghdl_bug11.vhdl:38:5:@81910001ps:(assertion error): expected = 2 actual = 0
ghdl:info: simulation stopped by --stop-time
Still showing the modulo 2047 effect on expected (val).
Providing an intial value for clk in a ghdl_bug3.vhdl variant
(ghdl_bug12.vhdl) likewise produces assertion reports because clk is then
running - the default value for bit is '0'.
I've found no evidence of a bug in ghdl. It seemed worth checking why a
contraindication was found during investigation (num to numeric_std). I
figured reporting it might prevent any one pointing out the apparent
inconsistency in my posts, the original comment left the issue dangling.
There are a couple of things I get out of this thread. First there isn't
good visibility into a ghdl simulation. You could note there's a lack of
general visibility into a ghdl simulation than what gtkwave outputting ghw
exhibits in this case. The only elements that shows up are clk and num.
While making a great argument for val being a signal it doesn't help debug
what you have.
It also makes a great argument for an interactive shell for GRT (the ghdl
runtime library), being able to run or step and perhaps things like
assertion markers in the waveform.
By definition ghdl isn't particularly friendly to these sort of bug hunts.
It's easy to demonstrate you can overlook clues you'd get visually with
other tool systems.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ghdl_bug is
port (
num : buffer unsigned(10 downto 0)
);
end entity;
architecture bug of ghdl_bug is
signal clk : std_logic;
begin
proc_clk : process is
begin
wait for 10 ns;
clk <= not clk;
end process;
proc_write : process is
begin
num <= (others => '0');
loop
wait until rising_edge(clk);
num <= num + 1;
end loop;
end process;
proc_read : process is
variable val : integer := 1;
begin
wait until rising_edge(clk);
wait for 1 ps;
assert(val = to_integer(num))
report "expected = " & integer'image(val) &
" actual = " & integer'image(to_integer(num));
val := val + 1;
if val = 2**11-1 then
val := 0;
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ghdl_bug is
port (
num : buffer unsigned(10 downto 0)
);
end entity;
architecture bug of ghdl_bug is
signal clk : std_logic;
begin
proc_clk : process is
begin
wait for 10 ns;
clk <= not clk;
end process;
proc_write : process is
begin
num <= (others => '0');
loop
wait until rising_edge(clk);
num <= num + 1;
end loop;
end process;
proc_read : process is
variable val : integer := 1;
begin
wait until rising_edge(clk);
wait for 1 ps;
assert(val /= to_integer(num))
report "expected = " & integer'image(val) &
" actual = " & integer'image(to_integer(num));
val := val + 1;
if val = 2**11-1 then
val := 0;
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
use ieee.numeric_std."+";
use ieee.numeric_bit.RISING_EDGE;
entity ghdl_bug is
port (
num : buffer unsigned(10 downto 0)
);
end entity;
architecture bug of ghdl_bug is
signal clk : bit;
begin
proc_clk : process is
begin
wait for 10 ns;
clk <= not clk;
end process;
proc_write : process is
begin
num <= (others => '0');
loop
wait until rising_edge(clk);
num <= num + 1;
end loop;
end process;
proc_read : process is
variable val : integer := 1;
begin
wait until rising_edge(clk);
wait for 1 ps;
assert(val = to_integer(num))
report "expected = " & integer'image(val) &
" actual = " & integer'image(to_integer(num));
val := val + 1;
if val = 2**11-1 then
val := 0;
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ghdl_bug is
port (
num : buffer unsigned(10 downto 0)
);
end entity;
architecture bug of ghdl_bug is
signal clk : std_logic := '0';
begin
proc_clk : process is
begin
wait for 10 ns;
clk <= not clk;
end process;
proc_write : process is
begin
num <= (others => '0');
loop
wait until rising_edge(clk);
num <= num + 1;
end loop;
end process;
proc_read : process is
variable val : integer := 1;
begin
wait until rising_edge(clk);
wait for 1 ps;
assert(val = to_integer(num))
report "expected = " & integer'image(val) &
" actual = " & integer'image(to_integer(num));
val := val + 1;
if val = 2**11-1 then
val := 0;
end if;
end process;
end architecture;
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