On Dec 12, 2011, at 9:17 AM, Serguey Zefirov wrote:
> I wrote a simple test for a "simple" entity. Entity is generated from
> some "high-level description".
>
> The test itself works fine, it reports a report and displays time. But
> when I add my entity, ghdl -r consumes 100% of one of my cores, leaks
> memory at the speed of about 1MB per second and displays nothing. No
> reports, no current time, nothing.
ghdl is single threaded.
>
> I tried various options, like --stop-delta=2. No use.
>
> Where should I look? Is there any tracing options?
You don't appear to provide enough information for providing any meaningful
help or insight on distinguishing between a tool environment issue, a VHDL
coding problem or a ghdl implementation issue.
On debugging ghdl:
4.2 Debugging VHDL programs
Debugging VHDL programs using GDB is possible only on GNU/Linux systems.
GDB is a general purpose debugger for programs compiled by GCC. Currently,
there is no VHDL support for GDB. It may be difficult to inspect variables or
signals in GDB, however, GDB is still able to display the stack frame in case
of error or to set a breakpoint at a specified line.
GDB can be useful to precisely catch a runtime error, such as indexing an array
beyond its bounds. All error check subprograms call the __ghdl_fatal procedure.
Therefore, to catch runtime error, set a breakpoint like this:
(gdb) break __ghdl_fatal
When the breakpoint is hit, use the where or bt command to display the stack
frames.
In lieu of an error indication you'd have to trap address pointers or actions
with gdb.
In lieu of that trying modifying your VHDL source to modify it's behavior.
Try VHDL that should work as a confidence builder. In the GHDL guide, Section 2
Starting with GHDL there's a hello world program that uses textio to write
"Hello World!" to standard output. It uses a wait statement right before the
end (process) statement to execute only once. removing that wait and doing
something to divert standard output could conceviable give you the sort of
behavior you're describing. Process statements inherently loop unless they
have a sensitivity list or a wait statement.
There can be variations with of hello world that use assertion or report
statements, an assertion statement allows the luxury of setting the severity
level, which can be used to stop simulation.
--assert-level=LEVEL stop simulation if assert at LEVEL
LEVEL is note,warning,error,failure,none
Perhaps you could use such a mechanism to break any 'out of control' loop?
Concurrent statements may not hit a delta of 2 if there are no uses of signals
on the right hand side.
You can see without a better idea of what you are doing the help is vague.
If your an absolute VHDL beginner a book might help, such as the recent 'Free
Range VHDL' a free book: www.freerangefactory.org/dl/free_range_vhdl.pdf
The purpose of this book is to provide students and young engineers with a
guide to help them develop the skills necessary to be able to use VHDL for
introductory and intermediate level digital design. These skills will also give
you the ability and the confidence to continue on with VHDL-based digital
design. n this way, you will also take steps toward developing the skills
required to implement more advanced digital design systems.
Otherwise if you can share a bit more it would be helpful.
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