2011/12/12 David Koontz <[email protected]>: > You don't appear to provide enough information for providing any meaningful > help or insight on distinguishing between a tool environment issue, a VHDL > coding problem or a ghdl implementation issue.
Okay, I attached problematic files.
runningSumMaybes.vhdl was created automatically.
runningSumMaybes_TB.vhdl is a testbench for runningSumMaybes.
The test is fine if you comment entity instantiation:
----------------------------------------------------------------------------
testing_entity: entity work.runningSumMaybes_1
port map(
maybeA_0 => maybe_word8_A,
currentSum_20 => current_sum,
Hardware_HHDL_Examples_Clock_Clk => clk,
Hardware_HHDL_Examples_Clock_Reset => rst
);
----------------------------------------------------------------------------
Without entity instantiation I get at least one report, so test works.
My friends told me that Aldec produces all three reports which is the
right answer.
runningSumMaybes.vhdl
Description: Binary data
runningSumMaybes_TB.vhdl
Description: Binary data
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