> I try as much as possible to use many of VHDL-2008's new features, > most of them are summarised in Jim's paper: > http://www.synthworks.com/papers/VHDL_2008_end_of_verbosity_2013.pdf > > Among the features taken from Jim's list, here's a list of the ones I > more frequently use (plus 1 or 2 additional): > > > 1. Simplified process sensitivity list.
I think it's already implemented (although not available). > 2. Simplified conditionals. Not implemented but not difficult to do. > 3. Reading out ports. Should be trivial. > 4. Enhanced bit string literals. Not difficult, but I'd like to improve the way bit string are handled. > 5. Expressions in port maps. My understanding is that this feature is broken: the anonymous signal add a delta delay which doesn't explicitly appear in the sources. Shouldn't be difficult to implement. > 6. Block commenting. Trivial. > 7. Matching relational operators, matching case statement. Shouldn't be difficult to implement. > Others that I also frequently use are some of the major enhancements > made in VHDL-2008, such as type generics, subprogram generics, and > package generics. Generics require deeper changes. Are you using 2008 style arrays ? Tristan. _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
