On 08/11/14 13:41, Adrien Prost-Boucle wrote:
Hi,
With at least the versions 0.31 and 0.32 of GHDL, I have some VHDL
designs for which simulation is extremely slow. By "extremely", I mean 1
cycle per minute. The same VHDL code is simulated at at least 1000
cycles/s with Xilinx's simulator.
Hello,
thank you very much for the reproducer, that's very useful.
I plan to work on performance issues for the next release, so your mail
is very welcome.
From a preliminary analysis, the issue is due to concatenation. Code
generated for concatenations could be improved!
Stay tuned.
Regards,
Tristan.
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