On 12/01/15 20:56, Torsten Meissner wrote:
I think the easiest „trick“ is to use an intermediate signal with 9 bits to
connect to oData
and then use only the 8 lower bits of it for HRDATA. That „problem" is a very
common one, you
will see the same solution in many generated code which uses FPGA internal
components with
fixed port widths like RAMs,
Indeed, GHDL is correct. See LRM93 4.3.2.2 Association lists:
Furthermore, every scalar subelement of the explicitly declared
interface object must be associated exactly once with an actual (or
subelement thereof) in the same association list, and all such
associations must appear in a contiguous sequence within that
association list.
So, the only way for GHDL to compile it is first to fix it, using eg a
dummy signal.
Regards,
Tristan.
Greets,
Torsten
Am 12.01.2015 um 20:46 schrieb Endre Bak <[email protected]>:
Hi,
I ran into a case which is Okay for Libero SoC but not Okay for GHDL.
I have the following component:
component RWRAM is
-- Delays are for nicer GHDL - gtkwave simulation
generic (
AssDelay : time := AssDelay;
RegDelay : time := RegDelay
);
port(
iClk : in std_logic;
-- read port
iRdAddr : in std_logic_vector(8 downto 0);
oData : out std_logic_vector(8 downto 0);
iRdEn : in std_logic;
-- write port
iWrAddr : in std_logic_vector(8 downto 0);
iData : in std_logic_vector(8 downto 0);
iWrEn : in std_logic
);
end component;
The width of oData is 9 bit but I want to assign only 8 of them. :
RAMGen: for i in 0 to 3 generate
RWRAMX: RWRAM port map (
iClk => HCLK,
-- read port
iRdAddr => HADDR(8 downto 0),
oData(7 downto 0) => HRDATA(8 * i + 7 downto 8 * i),
iRdEn => rdEn(i),
-- write port
iWrAddr => wrAddrReg, --HADDR(8 downto 0),
iData(8) => '0', iData(7 downto 0) => HWDATA(8 * i + 7 downto 8 *
i),
iWrEn => wrEnReg(i)
);
end generate RAMGen;
The tricky line is:
oData(7 downto 0) => HRDATA(8 * i + 7 downto 8 * i),
GHDL reports the following error:
AHBSlaveRAM.vhdl:78:29: no choice for 8
(Microsemi Libero SoC can synthesize it, just gives this message: @N: CD367
:"C:\Users\ebak\workspace.Libero\AHBSlaveRAM_Project\hdl\AHBSlaveRAM.vhd":70:2:70:7|Instance
RWRAMX, Port odata, Bit <8> connection not specified)
Is there any way in GHDL to make it compile?
Thanks,
Endre
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