Hello,
Le 2015-01-12 20:46, Endre Bak a écrit :
The tricky line is:
oData(7 downto 0) => HRDATA(8 * i + 7 downto 8 * i),
GHDL reports the following error:
AHBSlaveRAM.vhdl:78:29: no choice for 8
(Microsemi Libero SoC can synthesize it, just gives this message: @N:
CD367
:"C:Usersebakworkspace.LiberoAHBSlaveRAM_ProjecthdlAHBSlaveRAM.vhd":70:2:70:7|Instance
RWRAMX, Port odata, Bit <8> connection not specified)
Is there any way in GHDL to make it compile?
Thanks,
Endre
One thing I have not seen mentioned (or maybe my emails lag ?) is to use
"OPEN" :
oData(8) => open,
Does that work in that case ?
It only works on out or inout, so be careful, but it's better IMHO than
using a dummy signal because the dangling is explicit, so it might
generate less warnings.
Happy 2015 everybody !
_______________________________________________
Ghdl-discuss mailing list
[email protected]
https://mail.gna.org/listinfo/ghdl-discuss
