Hi, Here are the files. I have also included my results here: MyConsoleOutput.txt MyGhdlVersion.txt MyGtkWaveOutput.png
You can view the waves by executing: ./build.py viewFIFO Thanks! Endre On Sat, Feb 28, 2015 at 6:46 PM, Tristan Gingold <[email protected]> wrote: > On 28/02/15 00:05, Endre Bak wrote: > >> Hi, >> >> I ran into an issue which I cannot understand. I suspect it could be a >> bug in GHDL, of course it even can be that I am not aware of a very >> trivial coding issue of mine. >> > > Hello, > > yes, please send the file so that we can reproduce the issue. > > Tristan. > > >> I have two signals: >> >> signal writerClkCntInit: unsigned(1 downto 0) := "00"; >> signal writerClkCnt: unsigned(1 downto 0) := "00"; >> >> At the rising edge of the clock I make an assignment: >> >> report "writerClkCnt <= writerClkCntInit;"; >> writerClkCnt <= writerClkCntInit; >> >> It is also reflected on the console: >> >> TestFIFO.vhdl:109:24:@1500ns:(report note): rise >> TestFIFO.vhdl:78:32:@1500ns:(report note): writerClkCnt <= >> writerClkCntInit; >> >> In gtkwave, before 1500ns, both signal values are "00". After the >> assignment at 1500ns writerClkCnt becomes uninitialized and >> writerClkCntInit remains unchanged ("00"). >> >> What can cause such anomalies? May I send the files for analysis? >> >> Thanks, >> Endre >> >> >> _______________________________________________ >> Ghdl-discuss mailing list >> [email protected] >> https://mail.gna.org/listinfo/ghdl-discuss >> >> > > _______________________________________________ > Ghdl-discuss mailing list > [email protected] > https://mail.gna.org/listinfo/ghdl-discuss >
FIFO.tar.gz
Description: GNU Zip compressed data
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