Hello, I tested the FST output format. In GTKWave, the names of all std_logic signals miss their last character. The names of all vectors are correct.
To reproduce, the phony VHDL entity I sent in my previous message is enough (attached). Is this also an issue with GHDL, or is it GTKWave ? Regards, Adrien On Mon, 2015-03-09 at 08:36 +0100, Adrien Prost-Boucle wrote: > Hello, > > In fact it may be possible that any .ghw generated by GHDL is wrong. > > I wrote the attached VHDL file to test what we could do with the new, > great option, -gNAME=VALUE. > Simulation with ghw export produces wrong .ghw file. > Simulation with vcd export works fine. > > Regards, > Adrien > > > On Sat, 2015-03-07 at 14:58 +0100, Tristan Gingold wrote: > > On 07/03/15 09:17, Adrien Prost-Boucle wrote: > > > Hello, > > > > > > Yesterday evening in the GTKWave mailing list, Tony mentioned that in > > > GHDL there is an enum "skewed off by one in new versions of the code". > > > https://sourceforge.net/p/gtkwave/mailman/message/33556302/ > > > > I see. I will fix that. > > > > Regards, > > Tristan. > > > > > > > > Regards, > > > Adrien > > > > > > On Fri, 2015-03-06 at 20:39 +0100, Adrien Prost-Boucle wrote: > > >> Hello, > > >> > > >> I have a VHDL design that I compiled with GHDL. > > >> I launch simulation with command-line parameter --wave to have a ghw > > >> trace. However, when trying to open the .ghw file with gtkwave, I get > > >> the following error: > > >> > > >> ghw_read_type: unknown type 24 > > >> ghw_read_base: error in section TYP > > >> Error in ghw file 'lcm_bench.ghw'. > > >> > > >> On the GTKWave mailing list, they say it's GHDL fault. > > >> https://sourceforge.net/p/gtkwave/mailman/gtkwave-users/?viewmonth=201503 > > >> > > >> Attached is the faulty .ghw file. > > >> Unfortunately, I might not have the right to post the VHDL code, and > > >> it's large stuff. If the .ghw file is not enough to spot a bug, I'll see > > >> if I can produce a simple VHDL code that reproduces the error. > > >> > > >> Regards, > > >> Adrien > > >> > > >> _______________________________________________ > > >> Ghdl-discuss mailing list > > >> [email protected] > > >> https://mail.gna.org/listinfo/ghdl-discuss > > > > > > > > > > > > _______________________________________________ > > > Ghdl-discuss mailing list > > > [email protected] > > > https://mail.gna.org/listinfo/ghdl-discuss > > > > > > > > > _______________________________________________ > > Ghdl-discuss mailing list > > [email protected] > > https://mail.gna.org/listinfo/ghdl-discuss > > _______________________________________________ > Ghdl-discuss mailing list > [email protected] > https://mail.gna.org/listinfo/ghdl-discuss
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity phonybench is generic ( GENSTR : string := "adrien"; GENSTDLV : std_logic_vector(5 downto 0) := "111000"; GENSTDL : std_logic := '1'; GENNAT : natural := 22 ); end phonybench; architecture bench of phonybench is type char2std_t is array(character) of std_ulogic; constant char2std_c : char2std_t := ( 'U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'X' ); function str2std(arg : string) return std_logic_vector is variable result : std_logic_vector(arg'length - 1 downto 0); variable j : integer; begin j := arg'length - 1; for i in arg'range loop result(j) := char2std_c(arg(i)); j := j - 1; end loop; return result; end function; signal sigvec1 : std_logic_vector(5 downto 0) := str2std(GENSTR); signal sigvec2 : std_logic_vector(5 downto 0) := GENSTDLV; signal siglog : std_logic := GENSTDL; signal signat : natural := GENNAT; signal clk : std_logic := '0'; begin clk <= not clk after 5 ms; sigvec1 <= str2std(GENSTR); sigvec2 <= GENSTDLV; siglog <= GENSTDL; signat <= GENNAT; end architecture;
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