On 10/03/15 18:26, Adrien Prost-Boucle wrote:
Hello,
I tested the FST output format.
In GTKWave, the names of all std_logic signals miss their last
character. The names of all vectors are correct.
To reproduce, the phony VHDL entity I sent in my previous message is
enough (attached).
Is this also an issue with GHDL, or is it GTKWave ?
Hello,
both issues have been fixed (in GHDL).
Regards,
Tristan.
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