Hi, Recently I've been designing and simulating some complicated VHDL components, and I had a hard time finding the cause of GHDL error.
See attached VHDL code (simplified). In architecture of component "top", the declaration of the component "comp" does not match the definition of the component "comp". GHDL analyzes and elaborates with no problem. The error comes at run time: ./top:error: bound check failure at top.vhd:41 ./top:error: error during elaboration That line is where the instantiation of "comp" in "top" begins. So we don't know what signal/port/generic could trigger the error. Would it be possible to print the port name? Regards, Adrien
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity comp is port ( p0: in std_logic_vector(31 downto 0); p1: in std_logic_vector(31 downto 0); p2: in std_logic_vector(31 downto 0) ); end entity; architecture A of comp is begin end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity top is end entity; architecture A of top is signal sig0: std_logic_vector(31 downto 0); signal sig1: std_logic_vector(15 downto 0); signal sig2: std_logic_vector(31 downto 0); component comp is port ( p0: in std_logic_vector(31 downto 0); p1: in std_logic_vector(15 downto 0); p2: in std_logic_vector(31 downto 0) ); end component; begin i_comp : comp port map ( p0 => sig0, p1 => sig1, p2 => sig2 ); end architecture;
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