On 05/08/15 00:25, Adrien Prost-Boucle wrote:
Hi,
Recently I've been designing and simulating some complicated VHDL
components, and I had a hard time finding the cause of GHDL error.
See attached VHDL code (simplified).
In architecture of component "top", the declaration of the component
"comp" does not match the definition of the component "comp".
GHDL analyzes and elaborates with no problem. The error comes at run
time:
./top:error: bound check failure at top.vhd:41
./top:error: error during elaboration
That line is where the instantiation of "comp" in "top" begins.
So we don't know what signal/port/generic could trigger the error.
Would it be possible to print the port name?
Adrien,
can you create a ticket on sourceforge so that this won't be forgotten ?
Improving this error message shouldn't be very difficult, but I cannot
do that right now.
Thanks!
Tristan.
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